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IR3523 page 1 of 37 june 20, 2008 datasheet xphase3 tm dual output control ic description the IR3523 control ic provides a full featured and flexible way to implement a complete dual output dd r & cpu vtt multiphase power solution for intel vr11.1 motherboards. each output interfaces with any numbe r of xphase3 tm phase ics each driving and monitoring a single pha se. output 1 includes a 3 bit vr11.x vid, 1.1v boot voltage and droop to implement the cpu vtt rai l which is typically 1 phase. output 2 includes a 3 bit vid for margining and supports any number of phases and ddr dimm modules. the xphase3 tm architecture results in a power supply that is smaller, less expensive, and e asier to design while providing higher efficiency t han conventional approaches. independent features for both output 1 & 2 ? enable input ? power good (pg) output ? 0.5% overall system set point accuracy ? programmable softstart ? high speed error amplifier with wide bandwidth of 30mhz and fast slew rate of 12v/us ? remote sense amplifier provides differential sensi ng and requires less than 50ua bias current ? programmable over current threshold triggers const ant converter output current limit during start-up and hiccup protection during normal operation ? over voltage condition communicated to phase ics b y iin (ishare) and system by rosc/ovp pins ? detection and protection of open remote sense line s output 1 additional features ? 3 bit intel vr11.x vid (vid4, vid3, vid2) ? programmable vid offset ? 1.1 v boot voltage ? programmable output impedance ? programmable vid-on-the-fly slew rate output 2 additional features ? 3 bit vid provides 1.5 v with 150mv margining ? programmable vid-on-the-fly slew rate features shared by both outputs 1 & 2 ? programmable per phase switching frequency of 250k hz to 1.5mhz ? daisy-chain digital phase timing provides accurate phase interleaving without external components ? gate drive and ic bias linear regulator control wi th programmable output voltage and uvlo ? over voltage signal to system with over voltage de tection during powerup and normal operation ordering information device package order quantity IR3523mtrpbf 40 lead mlpq (6 x 6 mm body) 3000 per reel * IR3523mpbf 40 lead mlpq (6 x 6 mm body) 100 piece strips * samples only
IR3523 page 2 of 37 june 20, 2008 application circuit css/del1 cvdac1 css/del2 rvcclfb2 rosc rthermistor1 rvccldrv rfb13 phsout 32 enable2 4 enable1 5 vid2_0 38 iin2 6 ocset2 9 vosns1+ 17 vdrp1 26 pg2 37 iin1 25 clkout 31 vcclfb 35 vccl 34 phsin 33 vosns2- 15 eaout1 21 vout1 18 vdac1 23 vdac2 8 fb2 12 rosc/ovp 27 lgnd 29 vid1_4 1 fb1 19 vccldrv 36 ss/del1 24 vout2 13 ocset1 22 vonsn1- 16 vosns2+ 14 ss/del2 7 eaout2 10 vid1_3 2 vid1_2 3 nc 11 nc 20 nc 30 pg1 28 vid2_1 39 vid2_2 40 IR3523 control ic q1 vout2 sense + rocset1 vout2 sense - rvcclfb1 rvdac1 4.7uf cvccl pg2 to output 2 remote sense phsin 12v vid2_0 vid1_3 vout1 sense - vout1 sense + phsout pg1 rocset2 clkout vdac1 vid1_2 ishare1 eaout1 ccp21 ccp22 rcp2 vid1_4 12v cfb2 rfb21 rfb22 vid2_2 vid2_1 ovp flag 3 wire analog control bus to output 2 phase ics vccl to pow er stage to output 2 remote sense 3 w ire digital daisy chain bus to phase ics to phase ic vccl & gate drive bias enable 1 ishare2 enable 2 rvdac2 vref2 cvdac1 rcp1 ccp11 rfb11 cdrp1 rdrp1 cfb1 ccp12 rfb12 eaout2 3 wire analog control bus to output 1 phase ics load line ntc thermistor; locate close to output 1 pow er stage figure 1 ? IR3523 application circuit pin description pin# pin symbol pin description 1-3 vid1_4, vid1_3, vid1_2 vid inputs for output 1 4 enable2 enable input. a logic low applied to this pin puts output 2 into fault mode. a logic high signal on this pin enables output 2. do not float as the logic state will be undefined. 5 enable1 enable input. a logic low applied to this pin puts output 2 into fault mode. a logic high signal on this pin enables output 2. do not float as the logic state will be undefined. 6 iin2 output 2 average current input from the outp ut 2 phase ic(s). this pin is also used to communicate over voltage condition to the o utput 2 phase ics. 7 ss/del2 programs output 2 startup and over curren t protection delay timing. connect an external capacitor to lgnd to program. 8 vdac2 output 2 reference voltage. connect an exte rnal rc network to lgnd to provide compensation for the internal buffer amplif ier 9 ocset2 programs the output 2 constant converter o utput current limit and hiccup over- current threshold through an external resistor tied to vdac2 and an internal current source from this pin. over-current protecti on can be disabled by connecting a resistor from this pin to vdac2 to pro gram the threshold higher than the possible signal into the iin pin from the phase ics but no greater than 5v (do not float this pin as improper operation wil l occur). 10 eaout2 output 2 error amplifier output 11,20,30 nc no connection
IR3523 page 3 of 37 june 20, 2008 pin# pin symbol pin description 12 fb2 output 2 error amplifier inverting input 13 vout2 output 2 remote sense amplifier output. 14 vosen2+ output 2 remote sense amplifier input. c onnect to output at the load. 15 vosen2- output 2 remote sense amplifier input. c onnect to ground at the load. 16 vosen1- output 1 remote sense amplifier input. c onnect to ground at the load. 17 vosen1+ output 1 remote sense amplifier input. c onnect to output at the load. 18 vout1 output 1 remote sense amplifier output. 19 fb1 inverting input to the output 1 error amplif ier 21 eaout1 output 1 error amplifier output 22 ocset1 programs the output 1 constant converter output current limit and hiccup over- current threshold through an external resistor tied to vdac1 and an internal current source from this pin. over-current protecti on can be disabled by connecting a resistor from this pin to vdac1 to pro gram the threshold higher than the possible signal into the iin pin from the phase ics but no greater than 5v (do not float this pin as improper operation wil l occur). 23 vdac1 output 1 reference voltage programmed by t he vid inputs and error amplifier non-inverting input. connect an external rc network to lgnd to program dynamic vid slew rate and provide compensation for the internal buffer amplifier. 24 ss/del1 programs output 1 startup and over curre nt protection delay timing. connect an external capacitor to lgnd to program. 25 iin1 output 1 average current input from the out put 1 phase ic(s). this pin is also used to communicate over voltage condition to phase ics. 26 vdrp1 output 1 buffered iin signal. connect an e xternal rc network to fb1 to program converter output impedance. 27 rosc/ovp connect a resistor to lgnd to program o scillator frequency and ocset, vdac1 and vref2 bias currents. oscillator frequency equals switching frequency per phase. the pin voltage is 0.6v during normal operation and higher than 1.6v if over-voltage condition is detec ted. 28 pg1 open collector output. asserted when output 1 is regulated. 29 lgnd local ground for internal circuitry and ic substrate connection. 31 clkout clock output at switching frequency multi plied by phase number. connect to clkin pins of phase ics. 32 phsout phase clock output at switching frequency per phase. connect to phsin pin of the first phase ic. 33 phsin feedback input of phase clock. connect to phsout pin of the last phase ic. 34 vccl output of the voltage regulator, and power input for clock oscillator circuitry. connect a decoupling capacitor to lgnd. 35 vcclfb non-inverting input of the voltage regula tor error amplifier. output voltage of the regulator is programmed by the resistor divider con nected to vccl. 36 vccldrv output of the vccl regulator error ampli fier to control external transistor. the pin senses the converter input voltage through a re sistor. 37 pg2 open collector output. asserted when output 2 output is regulated. 38, 39, 40 vid2_0, vid2_1, vid2_2 vid inputs for output 2
IR3523 page 4 of 37 june 20, 2008 absolute maximum ratings absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. all vo ltages are absolute voltages referenced to the lgnd pin. operating junction temperature?????..0 to 150 o c storage temperature range???????.-65 o c to 150 o c esd rating???????????????hbm class 1c jedec standard msl rating???????????????2 reflow temperature???????????.260 o c pin # pin name v max v min i source i sink 1 vid1_4 8v -0.3v 1ma 1ma 2 vid1_3 8v -0.3v 1ma 1ma 3 vid1_2 8v -0.3v 1ma 1ma 4 enable2 3.5v -0.3v 1ma 1ma 5 enable1 3.5v -0.3v 1ma 1ma 6 iin2 8v -0.3v 5ma 1ma 7 ss/del2 8v -0.3v 1ma 1ma 8 vdac2 3.5v -0.3v 1ma 1ma 9 ocset2 8v -0.3v 1ma 1ma 10 eaout2 8v -0.3v 25ma 10ma 12 fb2 8v -0.3v 1ma 1ma 13 vout2 8v -0.5v 5ma 25ma 14 vosen2+ 8v -0.5v 5ma 1ma 15 vosen2- 1.0v -0.5v 5ma 1ma 16 vosen1- 1.0v -0.5v 5ma 1ma 17 vosen1+ 8v -0.5v 5ma 1ma 18 vout1 8v -0.5v 5ma 25ma 19 fb1 8v -0.3v 1ma 1ma 21 eaout1 8v -0.3v 25ma 10ma 22 ocset1 8v -0.3v 1ma 1ma 23 vdac1 3.5v -0.3v 1ma 1ma 24 ss/del1 8v -0.3v 1ma 1ma 25 iin1 8v -0.3v 5ma 1ma 26 vdrp1 8v -0.3v 35ma 1ma 27 rosc/ovp 8v -0.5v 1ma 1ma 28 pg1 8v -0.3v 1ma 20ma 29 lgnd n/a n/a 20ma 1ma 31 clkout 8v -0.3v 100ma 100ma 32 phsout 8v -0.3v 10ma 10ma 33 phsin 8v -0.3v 1ma 1ma 34 vccl 8v -0.3v 1ma 20ma 35 vcclfb 3.5v -0.3v 1ma 1ma 36 vccldrv 10v -0.3v 1ma 50ma 37 pg2 8v -0.3v 1ma 20ma 38 vid2_0 8v -0.3v 1ma 1ma 39 vid2_1 8v -0.3v 1ma 1ma 40 vid2_2 8v -0.3v 1ma 1ma
IR3523 page 5 of 37 june 20, 2008 recommended operating conditions for reliable opera tion with margin 4.75v vccl 7.5v, -0.3v vosen-x 0.3v, 0 o c t j 100 o c, 7.75 k rosc 50 k , css/delx = 0.1uf electrical characteristics the electrical characteristics involve the spread o f values guaranteed within the recommended operatin g conditions (unless otherwise specified). typical va lues represent the median values, which are related to 25c. parameter test condition min typ max unit system set point accuracy deviation from table 1 for output 1 and deviation from table 2 for output 2 per test circuit in figure 4a and 4b, respectively output 2 and output 1 output 2 at 1.8v (only) -0.5 -1.5 0.5 1.5 % % vidx interface increasing 0.85 .95 1.05 v decreasing (vid2_0 and vid2_1 only) 550 650 750 mv input thresholds hysteresis (vid2_0 and vid2_1 only) 190 300 410 mv pull-down resistance 100 175 250 k oscillator phsout frequency -10% see figure 2 +10% khz rosc voltage 0.575 0.600 0.625 v clkout high voltage i(clkout)= -10 ma, measure v(vc cl) ? v(clkout). 1 v clkout low voltage i(clkout)= 10 ma 1 v phsout high voltage i(phsout)= -1 ma, measure v(vcc l) ? v(phsout) 1 v phsout low voltage i(phsout)= 1 ma 1 v phsin threshold voltage compare to v(vccl) 30 50 70 % vdrp1 buffer amplifiers input offset voltage v(vdrp) ? v(iin), 0.5v v(iin) 3.3v -8 0 8 mv source current 0.5v v(iin1) 3.3v 2 30 ma sink current 0.5v v(iin1) 3.3v 0.2 0.4 0.6 ma unity gain bandwidth note 1 8 mhz slew rate note 1 4.7 v/ s iin bias current -1 0 1 a remote sense differential amplifiers unity gain bandwidth note 1 3.0 6.4 9.0 mhz input offset voltage 0.5v v(vosenx+) - v(vosenx-) 1.6v, note 2 -3 0 3 mv source current 0.5v v(vosenx+) - v(vosenx-) 1.6v 0.5 1 1.7 ma sink current 0.5v v(vosenx+) - v(vosenx-) 1.6v 2 12 18 ma slew rate 0.5v v(vosenx+) - v(vosenx-) 1.6v, note 1 2 4 8 v/us vosen+ bias current 0.5 v < v(vosenx+) < 1.6v 30 5 0 ua vosen- bias current -0.3v vosenx- 0.3v, all vid codes 30 50 ua low voltage v(vccl) = 7v 250 mv high voltage v(vccl) ? v(voutx) 0.5 1 v vdac1 & vdac2 outputs source currents includes i(ocset) -8% 3000*vrosc( v)/ rosc(k ) +8% a sink currents includes i(ocset) -11% 1000*vrosc v)/ rosc(k ) +11% a
IR3523 page 6 of 37 june 20, 2008 parameter test condition min typ max unit soft start and delay start delay measure enable to eaoutx activation 1 2.9 3.5 ms start-up time measure enable activation to pgx 3 8 13 ms oc delay time v(iinx) ? v(ocsetx) = 500 mv 200 650 1000 us ss/delx to fb input offset voltage with fb = 0v, adjust v(ss/del) until eaoutx drives high 0.7 1.4 1.9 v charge current -30 -50 -70 a oc delay discharge currents measure at charge volta ge 47 a fault discharge current 2.5 4.5 6.5 a hiccup duty cycle i(fault) / i(charge) 8 10 12 a/ a charge voltage (output 1,2) 3.5 3.9 4.2 v delay comparator threshold relative to charge volta ge, ss/delx rising - note 1 70 mv delay comparator threshold relative to charge volta ge, ss/delx falling - note 1 135 mv delay comparator hysteresis 65 mv vid1 sample delay comparator threshold 2.8 3.0 3.2 v discharge comp. threshold 150 200 300 mv error amplifiers input offset voltage measure v(fbx) ? v(vdacx)). n ote 2 25 o c t j 100 o c -1 0 1 mv fb1 bias current -5% vrosc(v)*100 0 /rosc(k ) +5% a fb2 bias current -1 0 1 a dc gain note 1 100 110 135 db bandwidth note 1 20 30 40 mhz slew rate note 1 5.5 12 20 v/ s sink current 0.4 0.85 1 ma source current 5.0 8.5 12.0 ma maximum voltage measure v(vccl) ? v(eaoutx) 500 780 950 mv minimum voltage 120 250 mv open control loop detection threshold measure v(vccl) - v(eaout), relative to error amplifier maximum voltage. 125 300 600 mv open control loop detection delay measure phsout pulse numbers from v(eaoutx) = v(vccl) to pgx = low. 8 pulse enable inputs threshold increasing 1.38 1.65 1.94 v threshold decreasing 0.8 0.99 1.2 v threshold hysteresis 470 620 800 mv bias current 0v v(x) 3.5v -5 0 5 ua blanking time noise pulse < 100ns will not register an enable state change. note 1 75 250 400 ns pgx outputs under voltage threshold - voutx decreasing reference to vdac -365 -315 -265 mv under voltage threshold - voutx increasing reference to vdac -325 -275 -225 mv under voltage threshold hysteresis 5 53 110 mv output voltage i(pgx) = 4ma 150 300 mv leakage current v(pgx) = 5.5v 0 10 a vccl_drv activation threshold i(pgx) = 4ma, v(pgx) < 400mv, v(vccl) = 0 1.0 2.0 3.6 v
IR3523 page 7 of 37 june 20, 2008 note 1: guaranteed by design, but not tested in production note 2: vdacx outputs are trimmed to compensate for error & amp remote sense amp input offsets parameter test condition min typ max unit over voltage protection (ovp) comparators threshold at power-up (output 2) 1.85 1.95 2.05 v threshold at power-up (output 1) 1.39 1.47 1.55 v voutx threshold voltage compare to v(vdacx) 100 12 5 150 mv ovp release voltage during normal operation compare to v(vdacx) -25 3 25 mv threshold during dynamic vid down (output 2) 1.87 1.93 1.99 v threshold during dynamic vid down (output 1) 1.24 1.33 1.37 v dynamic vid detect comparator threshold note 1 25 50 75 mv propagation delay to iin measure time from v(voutx) > v(vdacx) (250mv overdrive) to v(iinx) transition to > 0.9 * v(vccl). 90 180 ns ovp high voltage measure v(vccl)-v(rosc/ovp) 0 1.2 v ovp power-up high voltage v(vccldrv)=1.8v. measure v(vccl)- v(rosc/ovp) 0 0.2 v propagation delay to ovp measure time from v(voutx) > v(vdac) (250mv overdrive) to v(rosc/ovp) transition to >1v. 150 300 ns iin pull-up resistance 5 15 over-current comparators input offset voltage 1v v(ocsetx) 3.3v -35 0 35 mv ocset bias current -5% vrosc(v)*1000/ rosc(k ) +5% a 2048-4096 count threshold adjust rosc value to find threshold note 1 11.3 16 23.1 k 1024-2048 count threshold adjust rosc value to find threshold note 1 14.4 20 29.1 k open sense line detection sense line detection active comparator threshold voltage 150 200 250 mv sense line detection active comparator offset voltage v(voutx) < [v(vosen+) ? v(lgnd)] / 2 35 60 85 mv vosen+ open sense line comparator threshold compare to v(vccl) 86.5 89.0 91.5 % vosen- open sense line comparator threshold 0.36 0.40 0.44 v sense line detection source currents v(voutx) = 100mv 200 500 700 ua vccl regulator amplifier reference feedback voltage 1.15 1.2 1.25 v vcclfb bias current -1 0 1 ua vccldrv sink current 10 30 ma uvlo start threshold compare to v(vccl) 89.0 93.5 9 7.0 % uvlo stop threshold compare to v(vccl) 81.0 85.0 89 .0 % hysteresis compare to v(vccl) 7.0 8.25 9.5 % general vccl supply current 4 10 15 ma
IR3523 page 8 of 37 june 20, 2008 phsout frequency vs rrosc chart phsout frequency vs. rrosc 200 300 400 500 600 700 800 900 1000 1100 1200 1300 1400 1500 1600 5 10 15 20 25 30 35 40 45 50 55 rrosc (kohm) frequency (khz) figure 2 - phsout frequency vs. rrosc chart
IR3523 page 9 of 37 june 20, 2008 IR3523 block diagram 175k vdac2 uv2 ss/del1 175k + - 3.0v vid1 sample and delay comparator ov1 ov uv2 ssclf2 ssclf1 + - dly out1 vccldrv set dominant 50mv + - ov1 250ns blanking + - dynamic down vid2 internal vdac 1.0v vid2_2 vid2_1 ov1_2 vid2 vid3 vid2_0 vid0 vid1 vid2 vid3 uv1 + - vid input comparators (1 of 3 shown) s r q internal vdac digital to analog converters dynamic down vid1 1.0v vid1_3 vid1_4 vid1_2 vid3 vid0 vid2 vid3 vid1 vid2 s r q enable2 pg2 ov2 vboot ssclf2 pg2 ov1_2 + - 275mv 315mv vout2 uv comparator + - 275mv 315mv vout1 uv comparator set dominant uv cleared fault latch1 25k + - s r q open daisy dis idchg 4.5ua + - vdac2 vosen2- vosen2+ iin2 ocset2 fb2 eaout2 ss/del1 47ua vccl idchg1 vccl + - 3.9v ss/del cleared fault latch1 reset dominant power-up ok latch delay comparator set dominant discharge comparator 80mv 120mv ivosen- vidsel 0.2v oc1 after vrrdy irosc disable2 open sense1 ichg 50ua over voltage comparator vdac buffer amplifier error amplifier flt1 400k (1.1v) vdac1 dly out1 isink isource remote sense amplifier ivosen2- ivosen2+ 200mv 0.4v vccl*0.9 1.4v soft start clamp detection pulse1 125mv oc limit comparator 4 open sense line detect comparators 60mv vccl reset iocset open sense line2 0.3v vdac1 + - + - irosc s r q 47ua + - idchg2 s r q q open control2 pg1 + - 400k 25k ov + - dis vccl + - dis + - + - + + - + - + - 25k uv cleared fault latch2 set dominant + - vccl 25k + - s r q + - dis phsout dynamic vid1 down detect comparator 8 pulse delay irosc open control loop comparator open daisy phsout dly out1 dis idchg 4.5ua oc2 bf vrrdy vccl uvlo ov2 + - phsout clkout lgnd rosc phsin clkout fault phsin irosc phsout vid0 rosc buffer amplifier current source generator oc1 bf vrrdy open daisy chain 0.6v oc delay couter irosc dis reset reset phsout dis dis dis oc delay couter irosc dis dis phsout ov2 dly out2 fault latch 1 dly out2 s r q q 0.86 dchg1 dis vout2 vccl uvlo flt2 detection pulse1 ov1 + - + - 25k ss/del2 + - + - pg1 vdrp1 vccldrv vcclfb vccl enable1 vosen1- vosen1+ vout1 ocset1 fb1 eaout1 vdac1 iin1 vccl vccl disable1 ivosen- vidsel irosc irosc error amplifier delay comparator set dominant tbs ss/del cleared fault latch2 flt1 sample delay 1.65v 1.0v enable comparator vdac buffer amplifier vccl regulator amplifier over voltage comparator 250ns blanking vccl uvl comparator remote sense amplifier vdrp amplifier 0.94 1.2v power-up ok latch isink isource dis 50mv 0.2v discharge comparator 80mv 120mv reset dominant vidsel vccl*0.9 ivosen1- ivosen1+ 200mv 1.2v 0.4v soft start clamp ifb oc limit comparator 1.4v 4 open sense line detect comparators 60mv 125mv flt2 50ua open sense line1 oc2 after vrrdy dis detection pulse2 vdac2 iocset ichg 0.3v 8 pulse delay vccl reset internal circuit bias + - + - 25k ov dchg2 enable comparator + - 1.65v 1.0v + - open sense2 ovlatch + - + - vccl uvlo 25k + - 25k + - open control loop comparator vidsel vccl + - + - + s r q open control1 ov2 vccl uv1 ov1 1.8v dynamic vid2 down detect comparator set dominant dly out2 vccl - 1.2v figure 3 ? IR3523 block diagram
IR3523 page 10 of 37 june 20, 2008 system set point test converter output voltage is determined by the syste m set point voltage which is the voltage that appea rs at the fbx pins when the converter is in regulation. the s et point voltage includes error terms for the vdac digital-to- analog converters, error amp input offsets, and rem ote sense input offsets. the voltage appearing at t he vdacx pins is not the system set point voltage. system set point vol tage test circuits for outputs 1 and 2 are shown in figures 4a & 4b. isink isource vdac buffer amplifier ifb1 iocset1 current source generator rosc buffer amplifier 1.2v "fast" vdac irosc IR3523 system set point voltage remote sense amplifier error amplifier + - + - rrosc2 cvdac rvdac + - rocset + - fb1 ocset1 vdac1 vosen1+ vout1 lgnd rosc eaout1 irosc irosc vosen1- eaout vosns- figure 4a - output 1 system set point test circuit + - + - cvdac3 + - rvdac3 rrosc3 rocset3 + - fb2 eaout2 vosen2- vdac2 ocset2 rosc lgnd vout2 vosen2+ eaout irosc vosns- vdac buffer amplifier isink "fast" vdac 1.2v rosc buffer amplifier iocset1 system set point voltage IR3523 isource irosc error amplifier remote sense amplifier current source generator figure 4b - output 2 system set point test circuit
IR3523 page 11 of 37 june 20, 2008 system theory of operation pwm control method the pwm block diagram of the xphase3 tm architecture is shown in figure 5. feed-forward vo ltage mode control with trailing edge modulation is used. a high-gain wide-bandwidth voltage type error amplifier in the control ic is used for the voltage control loop. input voltage is sensed in phase ics and feed-forward control is re alized. the pwm ramp slope will change with the input voltage a utomatically compensating for changes in the input voltage. the input voltage can change due to variations in t he silver box output voltage or due to the wire and pcb-trace voltage drop related to changes in load current. figure 5 - pwm block diagram frequency and phase timing control the oscillator is located in the control ic and the system clock frequency is programmable from 500khz to 9mhz by an external resistor. the control ic system cloc k signal (clkout) is connected to clkin of all the phase ics. the phase timing of the phase ics is controlled by the daisy chain loop, where control ic phase clock output (phsout) is connected to the phase clock input (phs in) of the first phase ic, and phsout of the first phase ic is connected to phsin of the second phase ic, etc. and phsout of the last phase ic is connected back to p hsin of the control ic. during power up, the control ic sen ds out clock signals from both clkout and phsout pi ns and detects the feedback at phsin pin to determine the phase number and monitor any fault in the daisy cha in loop. figure 6 shows the phase timing for a four phase co nverter. gnd vout1 vosns1+ dacin vcc vdac1 vout1 iin1 vdrp1 lgnd ishare phsin vosns1- csin- csin+ gatel eain gateh sw vin fb1 eaout1 clkout clkin phsout pgnd vccl vcch dacin vcc clkin phsout csin+ gatel eain gateh ishare phsin sw pgnd vccl vcch csin- phsin phsout vid6 vid6 i rosc vid6 vid6 vid6 vid6 vid6 vid6 vid6 vid6 gate drive voltage - + + + enable ramp discharge clamp body braking comparator ifb1 vdrp1 amp vdac clock generator current sense amplifier r s share adjust error amplifier reset dominant pwm latch error amplifier cout IR3523 control ic phase ic output 1 only pwm comparator pwm comparator - + + + ramp discharge clamp enable body braking comparator share adjust error amplifier reset dominant pwm latch current sense amplifier r s phase ic remote sense amplifier ccs rcs + - cfb1 rcs cbst + - ccs cbst + - + - ccp11 + - + - rfb12 rdrp1 cdrp1 rfb11 3k + - + - clk d q + - + - rcp1 + - 3k + - + - ccp12 clk d q + -
IR3523 page 12 of 37 june 20, 2008 phase ic1 pwm latch set control ic clkout (phase ic clkin) control ic phsout (phase ic1 phsin) phase ic 1 phsout (phase ic2 phsin) phase ic 2 phsout (phase ic3 phsin) phase ic 3 phsout (phase ic4 phsin) phase ic4 phsout (control ic phsin) figure 6 - four phase oscillator waveforms pwm operation the pwm comparator is located in the phase ic. upon receiving the falling edge of a clock pulse, the p wm latch is set; the pwmrmp voltage begins to increase; the low side driver is turned off, and the high side drive r is then turned on after the non-overlap time. when the pwmr mp voltage exceeds the error amplifier?s output vol tage, the pwm latch is reset. this turns off the high side dr iver and then turns on the low side driver after th e non-overlap time; it activates the ramp discharge clamp, which quickly discharges the pwmrmp capacitor to the outp ut voltage of share adjust amplifier in phase ic until the nex t clock pulse. the pwm latch is reset dominant allowing all phases to go to zero duty cycle within a few tens of nano seconds in response to a load step decrease. phases can overla p and go up to 100% duty cycle in response to a loa d step increase with turn-on gated by the clock pulses. an error amplifier output voltage greater than the co mmon mode input range of the pwm comparator results in 100% d uty cycle regardless of the voltage of the pwm ramp . this arrangement guarantees the error amplifier is alway s in control and can demand 0 to 100% duty cycle as required. it also favors response to a load step decrease whi ch is appropriate given the low output to input vol tage ratio of most systems. the inductor current will increase mu ch more rapidly than decrease in response to load t ransients. this control method is designed to provide ?single cycle transient response? where the inductor curren t changes in response to load transients within a single switchi ng cycle maximizing the effectiveness of the power train and minimizing the output capacitor requirements. an additional advantage of the architecture is that differences in ground or input voltage at the phases have no effec t on operation since the pwm ramps are referenced t o vdac. figure 7 depicts pwm operating waveforms under vari ous conditions.
IR3523 page 13 of 37 june 20, 2008 phase ic clock pulse vdac eain pwmrmp gatel gateh duty cycle decrease due to vin increase (feed-forward) duty cycle increase due to load increase steady-state operation steady-state operation duty cycle decrease due to load decrease (body braking) or fault (vcc uv, ocp, vid fault) figure 7 - pwm operating waveforms body braking tm in a conventional synchronous buck converter, the m inimum time required to reduce the current in the i nductor in response to a load step decrease is; o min max slew v i i l t ) (* ? = the slew rate of the inductor current can be signif icantly increased by turning off the synchronous re ctifier in response to a load step decrease. the switch node v oltage is then forced to decrease until conduction of the synchronous rectifier?s body diode occurs. this inc reases the voltage across the inductor from vout to vout + v bodydiode . the minimum time required to reduce the current in the inductor in response to a load transient decrease is now; bodydiode o min max slew v v i i l t + ? = ) (* since the voltage drop in the body diode is often h igher than output voltage, the inductor current sle w rate can be increased by 2x or more. this patent pending techni que is referred to as ?body braking? and is accompl ished through the ?body braking comparator? located in th e phase ic. if the error amplifier?s output voltage drops below the vdac voltage or a programmable voltage, this co mparator turns off the low side gate driver. lossless average inductor current sensing inductor current can be sensed by connecting a seri es resistor and a capacitor network in parallel wit h the inductor and measuring the voltage across the capacitor, as shown in figure 8. the equation of the sensing netw ork is, cs cs l l cs cs l c c sr sl r s i c sr s v s v + + = + = 1 ) ( 1 1 ) ( ) ( usually the resistor rcs and capacitor ccs are chos en so that the time constant of rcs and ccs equals the time constant of the inductor which is the inductance l over the inductor dcr (r l ). if the two time constants match, the voltage across ccs is proportional to the current t hrough l, and the sense circuit can be treated as i f only a sense resistor with the value of r l was used. the mismatch of the time constants does not affect the measurement of inductor dc current, but affects the ac component o f the inductor current.
IR3523 page 14 of 37 june 20, 2008 figure 8 - inductor current sensing and current sen se amplifier the advantage of sensing the inductor current versu s high side or low side sensing is that actual outp ut current being delivered to the load is obtained rather than peak or sampled information about the switch curre nts. the output voltage can be positioned to meet a load lin e based on real time information. except for a sens e resistor in series with the inductor, this is the only sense me thod that can support a single cycle transient resp onse. other methods provide no information during either load i ncrease (low side sensing) or load decrease (high s ide sensing). an additional problem associated with peak or valle y current mode control for voltage positioning is t hat they suffer from peak-to-average errors. these errors will show in many ways but one example is the effect of freq uency variation. if the frequency of a particular unit is 10% low, the peak to peak inductor current will be 10% larger and the output impedance of the converter will drop by about 10%. variations in inductance, current sense amplifier bandwidth, pwm prop delay, any added slope compensa tion, input voltage, and output voltage are all add itional sources of peak-to-average errors. current sense amplifier a high speed differential current sense amplifier i s located in the phase ic, as shown in figure 8. it s gain is nominally 34 at 25oc, and the 3850 ppm/oc increase in inductor dcr should be compensated in the voltag e loop feedback path. the current sense amplifier can accept positive dif ferential input up to 50mv and negative up to -10mv before clipping. the output of the current sense amplifier is summed with the dac voltage and sent to the con trol ic and other phases through an on-chip 3k resistor connected to the ishare pin. the ishare p ins of all the phases are tied together and the voltage on the share bus repr esents the average current through all the inductor s and is used by the control ic for voltage positioning and curre nt limit protection. average current share loop current sharing between phases of the converter is achieved by the average current share loop in each phase ic. the output of the current sense amplifier is compar ed with average current at the share bus. if curren t in a phase is smaller than the average current, the share adjust amplifier of the phase will pull down the starting point of the pwm ramp thereby increasing its duty cycle and output c urrent; if current in a phase is larger than the av erage current, the share adjust amplifier of the phase will pull u p the starting point of the pwm ramp thereby decrea sing its duty cycle and output current. the current share amplifi er is internally compensated so that the crossover frequency of the current share loop is much slower than that of the voltage loop and the two loops do not interact. c o l r l r cs c cs v o current sense amp csout i l v l v cs c
IR3523 page 15 of 37 june 20, 2008 IR3523 theory of operation block diagram the block diagram of the IR3523 is shown in figure 3, and specific features are discussed in the follo wing sections. all the features are described using one output but suitable for both unless otherwise specified. vidx control the IR3523 converter outputs are independently cont rolled by two three-bit input interfaces (see table 1-2): vdac1 (vout1) and vdac2 (vout2). the vid codes are store d and then inputted to the digital-to-analog conver ter (dac) whose output is sent to the vdac buffer ampli fier. the output of the buffer amplifier is the vda c pin. vdac1 will initially boot to 1.1v when vout1 is ena bled then will transition to the stored vid1 value once ss/del1 reached 3.0 v. the vdac voltage, input offsets of error amplifier and remote sense differential ampli fier, are post- package trimmed to provide 0.5% system set-point accuracy. the actual vdac voltage does not determin e the system accuracy, which has a wider tolerance. the v id pins, vid2_x and vid1_x, require an external bia s voltage and should not be floated. the IR3523 can accept changes in the vid code while operating and vary dac voltage accordingly. the sink/source capability of the vdac buffer amplifier is programmed by the same external resistor that s ets the oscillator frequency. the slew rate of the voltage at the vdac pins can be adjusted by the external ca pacitors between vdac pins and lgnd pin. a resistor connecte d in series with this capacitor is required to comp ensate the vdac buffer amplifiers. the stepped vid transition results in a smooth analog transition of the vdac v oltage and converter output voltage. this analog transition m inimizes inrush currents in the input (and output) capacitors and reduces overshoot of the output voltage. vid1_4 vid1_3 vid1_2 vdac1 0 0 0 1.200 0 0 1 1.175 0 1 0 1.150 0 1 1 1.125 1 0 0 1.100 1 0 1 1.075 1 1 0 1.050 1 1 1 1.025 table 1: output (1) 3-bit vid table vid2_2 vid2_1 vid2_0 vdac2 0 0 0 1.350 0 0 1 1.400 0 1 0 1.450 0 1 1 1.500 1 0 0 1.550 1 0 1 1.600 1 1 0 1.650 1 1 1 1.800 table 2: output (2) 3-bit vid table
IR3523 page 16 of 37 june 20, 2008 output 1 (vtt) adaptive voltage positioning adaptive voltage positioning is needed to reduce th e output voltage deviations during load transients and the power dissipation of the load at heavy load. IR3523 only provides avp on output1. the circuitry related to t he voltage positioning is shown in figure 9. resistor r fb1 is connected between the error amplifier?s inverti ng input pin fb1 and the remote sense differential amplifier output. an internal current source whose value is programm ed by the same external resistor that programs the oscillator frequency sinks current from the fb1 pin. the erro r amplifier forces the converter?s output voltage higher to mai ntain a balance at its inputs. r fb1 is selected to program the desired amount of fixed offset voltage above the da c voltage. the vdrp1 pin voltage is a buffered reproduction of the iin1 pin which is connected to the current sha re bus ishare. the voltage on ishare represents the system average inductor current information. at each phas e ic, an rc network across the inductor provides current inf ormation which is gained up 32.5x and then added to the vdac x voltage. this phase current information is provided on the ishare bus via a 3k resistor in the phase i cs. the vdrp1 pin is connected to the fb1 pin through t he resistor r drp1 . since the error amplifier will force the loop to maintain fb1 to be equal to the vdac1 reference voltage, an additional current will flow into the f b1 pin equal to (vdrp1-vdac1) / r drp1 . when the load current increases, the adaptive pos itioning voltage increases accordingly. more current flows through the feedback resistor r fb1 , and makes the output voltage lower proportional t o the load current. the positioning voltage can be programmed by the resistor r drp1 so that the droop impedance produces the desired converter output impedance. the offset and slope of the converter output impedance are ref erenced to vdac1 and therefore independent of the vdac1 voltag e. vosen1- csin- csin+ iin1 csin- eaout1 ishare vdrp1 phase ic phase ic ishare vout1 + - rfb1 current sense amplifier + - 3k 3k rdrp1 + - ... ... + - vdac vdac remote sense amplifier vdac1 vdac1 fb1 ifb current sense amplifier error amplifier vdrp amplifier control ic vosen1+ csin+ + - figure 9 - adaptive voltage positioning
IR3523 page 17 of 37 june 20, 2008 output1 inductor dcr temperature compensation a negative temperature coefficient (ntc) thermistor can be used for output1 inductor dcr temperature compensation. the thermistor should be placed close to the output1 inductors and connected in parallel with the feedback resistor, as shown in figure 10. the resis tor in series with the thermistor is used to reduce the nonlinearity of the thermistor. + - eaout1 + - iin1 vdac1 ifb vdac1 control ic error amplifier rdrp1 vdrp amplifier vdrp1 rt rfb12 rfb11 fb1 vosen1+ vout1 vosen1- + - remote sense amplifier figure 10 - temperature compensation of output1 ind uctor dcr remote voltage sensing vosenx+ and vosenx- are used for remote sensing and connected directly to the load. the remote sense differential amplifiers with high speed, low input offset, and low input bias current ensure accurate voltage sensing and fast transient response. start-up sequence the IR3523 has a programmable soft-start function t o limit the surge current during the converter star t-up. a capacitor connected between the ss/delx and lgnd pi ns controls soft start timing, over-current protect ion delay and hiccup mode timing. a charge current of 50ua an d discharge currents of 47ua and 4.5ua control the up slope and down slope of the voltage at the ss/del pin res pectively.
IR3523 page 18 of 37 june 20, 2008 figure 11 depicts the start-up sequence. if the ena ble input is asserted and there are no faults, the ss/delx pins will start charging, the vid codes are read and sto red. vdac2 transitions to the stored vid code, whi le vdac1 transitions to a 1.1v internal boot voltage. the er ror amplifier output eaoutx is clamped low until ss /delx reaches 1.4 v. the error amplifier will then regulate the c onverter?s output voltage to match the ss/delx volt age less the 1.4 v offset until the converter vout2 reaches prog rammed vid code and vout1 reaches 1.1v (boot voltag e). when ss/del1 reaches 3.0 v, vdac1 will transition t o the stored vid1 code shifting vout1 to the new re gulation value. the ss/delx voltage continues to increase un til it rises above the threshold of delay comparato r (3.93v). the pgx output is then de-asserted (allowed to go h igh). vccl under voltage, over current, and a low signal on the enable input immediately sets a fault latch, which causes the eaout pin to drive low turning off the p hase ic drivers. the pgx pins also drives low and s s/delx begin to discharge until the voltage reaches 0.2 v. if the fault has cleared, the fault latch will be reset by the discharge comparator allowing a normal soft start t o occur. other fault conditions, such as over voltage, open sense lines, and open daisy chain, set different fa ult latches, which start discharging ss/delx, pull down eaoutx v oltage and drive pg low. however, the latches can o nly be reset by cycling vccl power (see table 3). if ss/delx pins are pulled below 0.6v, the converte r can be disabled. figure 11 - start-up sequence transition vid transition startup time (12v) start delay vcc enable 1.4v voutx pgx 3.92v ss/delx 4.0v normal operation vdacx vidx set voltage vid2 voltage eaoutx vid on - hold vid on - hold 0.5v vid on the fly procession 0.5v vid1_x vid2_x read & store read & store vid tansition 3.0v 1.1v boot (vout1 only) vout2 (no vboot) vout1 = vid1 ea1 ea2 1.1v boot (vout1) vid1 voltage shutdown
IR3523 page 19 of 37 june 20, 2008 over-current hiccup protection after soft start the over current limit threshold is set by a resist or connected between ocsetx and vdacx pins. figure 12 shows the hiccup over-current protection with delay after pgx is asserted. the delay is required since over- current conditions can occur as part of normal operation du e to load transients or vid transitions. if the iinx pin voltage, which is proportional to t he average current plus vdacx voltage, exceeds the ocsetx voltage after pgx is asserted, it will initiate the discharge of the capacitor at ss/delx through the discharge current 47ua. if the over-current condition persists long e nough for the ss/delx capacitor to discharge below the 120mv offset of the delay comparator, a fault latch will be set pulling the error amplifier?s output low and inhibiting switching in the phase ics and de-asserting the pgx signal. t he ss/del capacitor will then continue to discharge through a 4.7ua discharge current until it reaches 200 mv, an d the fault latch is reset allowing a normal soft s tart to occur. the output current is not controlled during the del ay time. if an over-current condition is again enco untered during the soft start cycle, the over-current action will repeat and the converter will be in hiccup mode. over-current protection (output shorted) normal operation 3.88v ea hiccup over-current protection (output shorted) power-down ocp delay start-up with output shorted normal operation 3.92v ss/del iout vout vrrdy 1.1v enable ocp threshold 4.0v normal start-up (output shorted) normal start-up figure 12 - hiccup over-current waveforms linear regulator output (vccl) the IR3523 has a built-in linear regulator contro ller, and only an external npn transistor is needed to create a linear regulator. the output voltage of the linear regulator can be programmed between 4.75v and 7.5v by the resistor divider at vcclfb pin. the regulator outpu t powers the gate drivers and other circuits of the phase ics along with circuits in the control ic, and the volt age is usually programmed to optimize the converter efficiency. the linear regulator can be compensated by a 4.7uf capa citor at the vccl pin. as with any linear regulator , due to stability reasons, there is an upper limit to the m aximum value of capacitor that can be used at this pin and it?s a function of the number of phases used in the multip hase architecture and their switching frequency. fi gure 13 shows the stability plots for the linear regulator with 5 phases switching at 750 khz.
IR3523 page 20 of 37 june 20, 2008 figure 13 - vccl regulator stability with 5 phases and phsout equals 750 khz vccl under voltage lockout (uvlo) the IR3523 has no under voltage lockout protection for the converter input voltage (vcc), but monitors the vccl voltage instead. the vccl is used to power both the control ic and phase ics including the phase ics i nternal gate drivers. during power up, the uvlo fault latch will be reset if vccl is above 94% of the voltage set b y resistor divider at vcclfb pin. if vccl voltage drops below 86% of the set value, the uvlo fault latch will be set. power good (pg1, 2) the pgx pin is an open-collector output and should be pulled up to a voltage source through a resistor . during soft start, the pgx remains low until the output voltage is in regulation and ss/delx is above 3.93v. the p gx pin becomes low if any of the fault latches are trigger ed (see table 3). pgx monitors the output voltage. if any of the volt age planes fall out of regulation, pgx will become low, but the vr will continue to attempt to regulate the output vol tages. output voltage out of spec is defined as 315 mv to 275mv below nominal voltage. vid on-the-fly transition, w hich is a voltage plane transitioning between two d ifferent vid codes, is not considered to be out of specification . a high level at the pgx pins indicates that the con verter is in operation with no fault and ensures th e output voltage is within the regulation. the pg outputs derive power from either vccl or vcc ldrv to ensure they can assert with input voltage a s low as possible. open control loop detection the error amplifier?s output voltage is monitored t o ensure the control loop is in regulation. if any fault condition forces the error amplifier output above vccl-1.08 v for 8 switching cycles, the open control loop faul t latch is set. this fault latch can only be cleared by cycling pow er to vccl. load current indicator output the vdrp pin voltage represents the average current of the converter plus the vdac1 voltage. the load current information can be retrieved by using a differentia l amplifier to subtracts the vdac1 voltage from the vdrp1 voltage.
IR3523 page 21 of 37 june 20, 2008 enable input pulling the enable pin below 1.0 v sets the fault l atch. forcing enable to a voltage above 1.65v resu lts in the 3-bit vid codes to be read and stored. ss/del x pins are also allowed to begin their power-up cycl es as long as no fault conditions are present. over voltage protection (ovp) output over-voltage might occur due to a high side mosfet short or if the output voltage sense path is compromised. if the over-voltage protection compara tors sense that either vout x pin voltage exceeds vdac x by 125mv, the over voltage fault latch is set which pu lls the error amplifier output low turning off both converters power stage. the IR3523 communicates an ovp condition to the system by raising the rosc pin voltage to withi n v(vccl) ? 1.2 v. an ovp condition is also communic ated to the phase ics by forcing the iin pin (which is tied to the ishare bus and ishare pins of the phase ics) to vccl as shown in figure 14. in each phase ic, the ovp circuit overrides the normal pwm operation to ensur e the low side mosfet turn-on within approximately 130ns. the low side mosfet will remain on until the ishare pins fall below v(vccl) - 800mv. an over voltage fault condition is latched in the IR3523 and can only be cleared by cycling the power to vccl. during dynamic vid down at light to no load, false ovp triggering is prevented by increasing the ovp t hreshold to a fixed 1.2 v (vout1) and 1.8 v (vout2) whenever a dy namic vid is detected and the difference between ou tput voltage and the fast internal vdac is more than 50m v, as shown in figure 15. the over-voltage threshol d is changed back to vdac+125mv if the difference betwee n output voltage and the fast internal vdac is less than 50mv. the overall system must be considered when designin g for ovp. in many cases the over-current protectio n of the ac-dc or dc-dc converter supplying the multiphase c onverter will be triggered thus providing effective protection without damage as long as all pcb traces and compon ents are sized to handle the worst-case maximum cur rent. if this is not possible, a fuse can be added in the in put supply to the multiphase converter. after ovp fault latch output voltage (vout) ovp threshold iin (phase ic ishare) vccl-800 mv ovp condition normal operation gateh (phase ic) gatel (phase ic) error amplifier output (eaout) vdac figure 14 - over-voltage protection during normal o peration
IR3523 page 22 of 37 june 20, 2008 output voltage (vo) vid down normal operation vdac vid ov threshold vdac + 130mv 1.73v normal operation vid up low vid vdac 50mv 50mv figure 15 - over-voltage protection during dynamic vid open remote sense line protection if either remote sense line vosen x + or vosen x - is open, the output of remote sense amplifier (vo ut x ) drops. the IR3523 continuously monitors the vout x pin and if vout x is lower than 200 mv, two separate pulse currents are applied to the vosen x + and vosen x - pins to check if the sense lines are open. if vos en x + is open, a voltage higher than 90% of v(vccl) will be present at vosen x + pin and the output of open line detect comparator will be high. if vosen x - is open, a voltage higher than 400mv will be pres ent at vosen x - pin and the open line detect comparator output will be high. with either sense line open, the open sense line fault latch wi ll be set to force the error amplifier output low and immediatel y shut down the converter. ss/del x will be discharged and the open sense fault latch can only be reset by cycling the power to vccl. open daisy chain protection IR3523 checks the daisy chain every time it powers up. it starts a daisy chain pulse on the phsout pin and detects the feedback at phsin pin. if no pulse come s back after 32 clkout pulses, the pulse is restart ed again. if the pulse fails to come back the second time, the o pen daisy chain fault is registered, and ss/del is not allowed to charge. the fault latch can only be reset by cyclin g the power to vccl. after powering up, the IR3523 monitors phsin pin fo r a phase input pulse equal or less than the number of phases detected. if phsin pulse does not return within the number of phases in the converter, another pulse i s started on phsout pin. if the second started phsout pulse does not return on phsin, an open daisy chain fault is registered. phase number determination after a daisy chain pulse is started, the IR3523 ch ecks the timing of the input pulse at phsin pin to determine the phase number.
IR3523 page 23 of 37 june 20, 2008 the fault table below describes ten different fault s that can occur during normal operation and how th e IR3523 ic will react to protect the supply and the load from possible damage. the fault types that can occur are listed in row one. row two and three describes the type and the m ethod of clearing the faults, respectively. the fir st four faults are latched in the uv fault and require the vccl su pply to be recycled (below uvlo threshold) to regai n operation. the rest of the faults, except for uvlo vout, are l atched in a ss fault which do not need vccl supply recycled, but instead will automatically resume operation when th ese fault conditions are no longer impinging on the system. most of the faults will disable the error amplifier (ea) and discharge the soft start capacitor. all o f the faults flag pgood. pgood returns to high impedance state (high) when the fault clears. the delay row shows reactio n time after detecting a fault condition. delays are provi ded to minimize the possibility of nuisance faults. additional flagged responses are used to communicate externally of a f ault event (over voltage) so additional action can be taken. system fault table fault type open daisy open sense open control over voltage disable uvlo (vccl) oc before oc after uvlo (vout) latch uv latch ss latch no fault clearing method recycle vccl ss discharge below 0.2v no outputs affected both single both both both single single error amp disables yes no ss/delx discharge yes no flags pgood yes delays 32 clock pulses no 8 phsout pulses no 250ns blanking time no phsout pulses* ss/delx discharge threshold no additional flagged response no yes, iinx and rosc pins pulled-up to vccl** no * pulse number range depends on rosc value selected (see specifications table) ** clears when ov condition ends table 3 - IR3523 system fault responses
IR3523 page 24 of 37 june 20, 2008 applications information psi_ph5 c207 r94 2 5 4 1 3 6 7 q33 c209 c2 1 0 c211 c212 c214 vdac_vddr3 ea_vddr3 p12v_ddr3_filted vcc 16 sw 15 gateh 14 nc3 20 phsin 5 vccl 12 pgnd 9 dacin 3 phsout 7 gatel 10 nc1 6 psi 2 iout 1 lgnd 4 clkin 8 boost 13 csin+ 17 csin- 18 eain 19 nc2 11 u80 1 2 l27 2 5 4 1 3 6 7 q34 IR3523 control ic vtt_sen+ ir3505 phase ic psi_ph5 vccl vtt_sen+ c189 r92 2 5 4 1 3 6 7 q29 c191 c193 c1 9 2 c194 c197 vdac_vddr3 ea_vddr3 p12v_ddr3_filted vcc 16 sw 15 gateh 14 nc3 20 phsin 5 vccl 12 pgnd 9 dacin 3 phsout 7 gatel 10 nc1 6 psi 2 iout 1 lgnd 4 clkin 8 boost 13 csin+ 17 csin- 18 eain 19 nc2 11 u74 2 5 4 1 3 6 7 q30 1 2 l24 vccl cout vid_ddr3_1 r72 vid_ddr3_0 r77 r67 r78 r80 c378 r75 r73 c138 r76 vddr3_sen+ vtt_sen+ cout vddr3- vddr3+ vtt_sen- vddr3_sen- vtt_sen+ c377 q16 r54 vtt_sen- r55 c135 c131 p12v_ddr3_filted vccl vdac_vtt ea_vddr3 r56 c137 c374 vtt+ r68 r70 r65 c375 vid_vtt_2 vid_vtt_4 vid_vtt_3 c376 vid1_4 1 vid1_3 2 vid1_2 3 enable2 4 enable1 5 iin2 6 ss/del2 7 vdac2 8 ocset2 9 eaout2 10 nc1 11 fb2 12 vout2 13 wosen2+ 14 vosen2- 15 vosen1- 16 vosen1+ 17 vout1 18 fb1 19 nc2 20 eaout1 21 ocset1 22 vdac1 23 ss/del1 24 iin1 25 vdrp1 26 rosc/ovp 27 pg1 28 lgnd 29 nc3 30 vid2_2 40 vid2_1 39 vid2_0 38 pg2 37 vccldrv 36 vcclfb 35 vccl 34 phsin 33 phsout 32 clkout 31 pad 41 u1 c142 no stuf f enable_ddr3 enable_vtt vtt_sen- vddr3_sen+ r69 c136 c379 vtt_vrrdy c380 c381 vddr3_vrrdy r71 r66 r243 vid_ddr3_2 r244 vdac_vddr3 c139 vddr3_sen- vtt- ir3508 phase ic c244 eain 16 csin+ 14 vcc 13 csin- 15 phsout 5 gateh 11 vccl 9 lgnd 3 pgnd 7 boost 10 clkin 6 ishare 1 dacin 2 phsin 4 gatel 8 sw 12 u71 r100 c188 1 2 l30 vtt_sen- c187 c186 c1 8 2 vdac_vtt p12v_cpu_filted vccl 2 5 4 1 3 6 7 q27 2 5 4 1 3 6 7 q28 psi_ph5 c198 vccl r93 2 5 4 1 3 6 7 q31 c200 c203 c202 c205 ea_vddr3 p12v_ddr3_filted vdac_vddr3 vcc 16 sw 15 gateh 14 nc3 20 phsin 5 vccl 12 pgnd 9 dacin 3 phsout 7 gatel 10 nc1 6 psi 2 iout 1 lgnd 4 clkin 8 boost 13 csin+ 17 csin- 18 eain 19 nc2 11 u79 2 5 4 1 3 6 7 q32 1 2 l25 ir3508 phase ic ir3508 phase ic figure 16 - IR3523 \ ir3508 three phases vddr3 and a single p hase (ir3505) vtt one phase converter
IR3523 page 25 of 37 june 20, 2008 design procedures - IR3523 and ir3505 chipset IR3523 external components all the output components are selected using one ou tput but suitable for both unless otherwise specifi ed. oscillator resistor rosc the IR3523 generates square-wave pulses to synchron ize the phase ics. the switching frequency of the e ach phase converter equals the phsout frequency, which is set by the external resistor r rosc , use figure 2 to determine the r rosc value. the clkout frequency equals the switching fr equency multiplied by the phase number. soft start capacitor c ss/del the soft start capacitor c ss/del programs four different time parameters, soft star t delay time, soft start time, pgx delay time and over-current fault latch delay t ime after pgx. ss/delx pin voltage controls the slew rate of the c onverter output voltage, as shown in figure 10. onc e the enable pin rises above 1.65v, there is a soft-start delay time td1 during which ss/del pin is charged from zero to 1.4v. once ss/del reaches 1.4v, the error a mplifier output is released to allow the soft start . the soft start time, td2, represents the time during which c onverter voltage rises from zero to vid2 or vout1?s boot voltage (1.1v). the ss/delx pins voltage rises fro m 1.4v to vid2 (or vout1 boot) plus 1.4v. power goo d delay time, td3, is the time period from between where vr reaches the vid voltage and pgx signal assertion. calculate c ss/del based on the required soft start time td2. vid td vid i td c chg del ss 6 / 10 * 50 * 2 * 2 ? = = (1) the soft start delay time td1 and vr ready delay ti me td3 are determined by equation (2) and (3) respe ctively. 6 / / 10 * 50 4.1 * 4.1 * 1 ? = = del ss chg del ss c i c td (2) 6 / / 10 * 50 )4.1 93.3(* )4.1 93.3(* 3 ? ? ? = ? ? = vid c i vid c td del ss chg del ss (3) once c ss/del is chosen, use equation (4) to calculate the maxim um over-current fault latch delay time t ocdel. 6 / / 10 * 47 12.0 * 5.2 12.0 * 5.2 ? ? = ? = del ss dischg del ss ocdel c i c t (4) due to the exponential turn-on slope of the dischar ge current (47ua), a correction factor (x2.5) is ad ded to the equation (4) to accurately predict over-current del ay time.
IR3523 page 26 of 37 june 20, 2008 vdac slew rate programming capacitor c vdac and resistor r vdac the slew rate of vdacx down-slope sr down can be programmed by the external capacitor c vdac as defined in (5), where i sink is the sink current of vdac pin. the slew rate of v dac up-slope is three times greater that of down-slope. the resistor r vdac is used to compensate vdac circuit and is determin ed by (6). down sink vdac sr i c = (5) 2 15 10 2.3 5.0 vdac vdac c r ? ? + = (6) over current setting resistor r ocset the inductor dc resistance is utilized to sense the inductor current. the copper wire of inductor has a constant temperature coefficient of 3850 ppm/c, and therefo re the maximum inductor dcr can be calculated from (7), where r l_max and r l_room are the inductor dcr at maximum temperature t l_max and room temperature t l _ room respectively. )] ( 10 * 3850 1[ _ _ 6 _ _ room l max l room l max l t t r r ? ? + ? = ? (7) the total input offset voltage (v cs_tofst ) of current sense amplifier in phase ics is the su m of input offset (v cs_ofst) of the amplifier itself and that created by the am plifier input bias current flowing through the curr ent sense resistor r cs . cs csin ofst cs tofst cs r i v v ? + = + _ _ (8) the over current limit is set by the external resis tor r ocset as defined in (9). i limit is the required over current limit. i ocset is the bias current of ocset pin and can be calcul ated with the equation in the electrical characteristics table. g cs is the gain of the current sense amplifier. k p is the ratio of inductor peak current over average current in each phase and can be calcu lated from (10). ocset cs tofst cs p max l limit ocset i g v k r n i r / ] ) 1( [ _ _ ? + + ? ? = (9) n i f v l v v v k o sw i o o i p / )2 /( ) ( ? ? ? ? ? = (10) vccl programming resistor r vcclfb1 and r vcclfb2 since vccl voltage is proportional to the mosfet ga te driver loss and inversely proportional to the mosfet conduction loss, the optimum voltage should be chosen to maximize the converter efficiency. vcc l linear regulator consists of an external npn transi stor, a ceramic capacitor and a programmable resist or divider. pre-select r vcclfb1 , and calculate r vcclfb2 from (11). 23.1 23.1 * 1 2 ? = vccl r r vcclfb vcclfb (11)
IR3523 page 27 of 37 june 20, 2008 no load offset setting resistor rfb11, rfb13, rtherm1 and adaptive voltage positioning resistor rdrp11 for output1 define r fb_r is the effective offset resistor at room temperatur e equals to r fb11 //(r fb13 +r therm1 ). given the offset voltage v o_nlofst above the dac voltage, calculate the sink current f rom the fb1 pin i fb1 using the equation in the electrical characteristics table, t hen the effective offset resistor value r fb1 can be determined from (12). 1 _ _ fb nlofst o r fb i v r = (12) adaptive voltage positioning lowers the converter v oltage by r o *i o, where r o is the required output impedance of the converter. pre-select feedback resistor r fb, and calculate the droop resistor rdrp, o cs room l r fb drp r n g r r r ? ? = * _ _ 11 (13) calculate the desired effective feedback resistor a t the maximum temperature r fb_m using (14) max l cs o drp m fb r g n r r r _ 11 _ * ? ? = (14) a negative temperature constant (ntc) thermistor r therm1 is required to sense the temperature of the power stage for the inductor dcr thermal compensation. pr e-select the value of r therm. r therm must be bigger than r fb_r at room temperature but also bigger than r fb_m at the maximum allowed temperature. r tmax1 is defined as the ntc thermistor resistance at maximum allowed temperature, t max. r tmax1 is calculated from (15). )] 1 1 (* [ * _ _ 1 1 1 room max l therm therm tmax t t b exp r r ? = (15) select the series resistor r fb13 by using equation (16). r fb13 is incorporated to linearize the ntc thermistor which has non-linear characteristics in the operati onal temperature range. 2 ) ( )) /( * * ) ( * ( * 4 ) ( 1 1 _ _ _ _ 1 1 1 1 2 1 1 13 tmax therm m fb r fb m fb r fb tmax therm tmax therm tmax therm fb t r r r r r r r r r r r r + ? ? ? ? ? + = (16) use equation (17) to determine r fb11. 1 13 _ 11 1 1 1 therm fb r fb fb r r r r + ? = (17)
IR3523 page 28 of 37 june 20, 2008 voltage loop compensation the adaptive voltage positioning (avp) is usually a dopted in the computer applications to improve the transient response and reduce the power loss at heavy load. l ike current mode control, the adaptive voltage posi tioning loop introduces extra zero to the voltage loop and splits the double poles of the power stage, which m ake the voltage loop compensation much easier. adaptive voltage positioning lowers the converter v oltage by r o *i o, where r o is the required output impedance of the converter. the selection of compensation types depends on the output capacitors used in the converter. for the ap plications using electrolytic, polymer or al-polymer capacitor s and running at lower frequency, type ii compensat ion shown in figure (a) is usually enough. while for the appl ications using only ceramic capacitors and running at higher frequency, type iii compensation shown in figure 21 (b) is preferred. for applications where avp is not required, the com pensation is the same as for the regular voltage mo de control. for converter using polymer, al-polymer, a nd ceramic capacitors, which have much higher esr z ero frequency, type iii compensation is required as sho wn in figure 21(b) with r drp and c drp removed. rcp ccp1 eaout ccp rfb rdrp vo+ vdrp vdac + - eaout fbfb cfb cdrp rcp eaout ccp1 ccp rfb rdrp vo+ vdrp vdac fb + - eaout rfb1 (a) type ii compensation (b) type iii compensation figure 17 - voltage loop compensation network type ii compensation for avp applications determine the compensation at no load, the worst ca se condition. choose the crossover frequency fc bet ween 1/10 and 1/5 of the switching frequency per phase. assume the time constant of the resistor and capaci tor across the output inductors matches that of the inductor, and determine r cp and c cp from (23) and (24), where l e and c e are the equivalent inductance of output inductors and the equivalent capacitance of output capacitors respectively. 2 2 ) * * * 2( 1 * 5 ) 2( c c i fb e e c cp r c f v r c l f r + ? ? ? ? ? = (23) cp e e cp r c l c ? ? = 10 (24) c cp1 is optional and may be needed in some applications to reduce the jitter caused by the high frequency noise. a ceramic capacitor between 10pf and 220pf is usual ly enough.
IR3523 page 29 of 37 june 20, 2008 type iii compensation for avp applications determine the compensation at no load, the worst ca se condition. assume the time constant of the resis tor and capacitor across the output inductors matches that of the inductor, the crossover frequency and phase margin of the voltage loop can be estimated by (25) and (26), where r le is the equivalent resistance of inductor dcr. le fb cs e drp c r r g c r f ? ? = * * 2 1 (25) 180 )5.0 tan( 90 1 ? ? = a c (26) choose the desired crossover frequency fc around fc 1 estimated by (25) or choose fc between 1/10 and 1 /5 of the switching frequency per phase, and select the c omponents to ensure the slope of close loop gain is -20db /dec around the crossover frequency. choose resisto r r fb1 according to (27), and determine c fb and c drp from (28) and (29). fb fb r r 2 1 1 = to fb fb r r 3 2 1 = (27) 1 4 1 fb c fb r f c ? ? = (28) drp fb fb fb drp r c r r c ? + = ) ( 1 (29) r cp and c cp have limited effect on the crossover frequency, an d are used only to fine tune the crossover frequency and transient load response. determine r cp and c cp from (30) and (31). i fb e e c cp v r c l f r 5 ) 2( 2 ? ? ? ? ? = (30) cp e e cp r c l c ? ? = 10 (31) c cp1 is optional and may be needed in some applications to reduce the jitter caused by the high frequency noise. a ceramic capacitor between 10pf and 220pf is usual ly enough. type iii compensation for non-avp applications resistor r drp and capacitor c drp are not needed. choose the crossover frequency fc between 1/10 and 1/5 of the switching frequency per phase and select the de sired phase margin c. calculate k factor from (32), and determine the component values based on (33) to (37 ), )]5.1 180 ( 4 tan[ + ? = c k (32) k v f c l r r i c e e fb cp ? ? ? ? ? ? = 5 ) 2( 2 (33) cp c cp r f k c ? ? = 2 (34) cp c cp r k f c ? ? ? = 2 1 1 (35)
IR3523 page 30 of 37 june 20, 2008 fb c fb r f k c ? ? = 2 (36) fb c fb c k f r ? ? ? = 2 1 1 (37) current share loop compensation the internal compensation of current share loop ens ures that crossover frequency of the current share loop is at least one decade lower than that of the voltage loop so t hat the interaction between the two loops is elimin ated. design example ? three phase (ddr) and one phase (v tt) converter (figure 16) specifications: input voltage: v i = 12 v dac1 voltage: v dac1 = 1.22 v dac2 voltage: v dac2 = 1.5 v no load output voltage offset for output1: v o_nlofst = 20 mv output1 current: i o1 = 28a dc output2 current: i o2 = 85a dc output1 over current limit: i limit1 =42a dc output2 over current limit: i limit2 = 125a dc output1 impedance: r o1 = 6.0 m dynamic vid slew rate rise: sr = 3.25mv/us over temperature threshold: t max = 110 oc power stage: phase number: n1 = 1, n2 = 3 switching frequency: f sw = 750 khz output inductors: l1 = 150 nh, l2 = 90nh, r l1 = 0.47m , r l2 = 0.47m output capacitors: ceramics, c = 22uf, r c = 1.5 m , number cn1 = 15, cn2 = 6 output capacitors: ceramics, c = 10uf, r c = 1 m , number cn1 = 0, cn2 = 70 (10 per dimm) oscillator resistor r rosc once the switching frequency is chosen, r rosc can be determined from figure 2. for switching frequency of 750 khz per phase, choose r osc = 15.8 k .
IR3523 page 31 of 37 june 20, 2008 soft start capacitor c ss/del determine the soft start capacitor from the require d soft start time. uf vboot i td c chg del ss 1.0 1 . 1 10 * 50 * 10 * 2 * 2 1 6 3 / = = = ? ? uf vid i td c chg del ss 1.0 5 . 1 10 * 50 * 10 * 2 2 * 2 2 6 3 / = = = ? ? the soft start delay time is ms i c td chg del ss 8.2 10 * 50 4.1 * 10 * 1.0 4.1 * 1 6 6 / = = = ? ? the power good delay time is ms i v c td chg boot del ss 9.2 10 * 50 )4.1 1.1 93.3(* 10 * 1.0 )4.1 93.3(* )1(3 6 6 1 / = ? ? = ? ? = ? ? ms i vid c td chg del ss 0.2 10 * 50 )4.1 5.1 92.3(* 10 * 1.0 )4.1 2 92.3(* )2(3 6 6 2 / = ? ? = ? ? = ? ? the maximum over current fault latch delay time is ms i c t dischg del ss ocdel 638 .0 10 * 47 12.0 * 10 * 1.0 * 5.2 12.0 * * 5.2 6 6 / = = = ? ? vdac slew rate programming capacitor c vdac and resistor r vdac nf sr i c down source vdac 7. 34 10 * 25.3 10 113 3 6 = ? = = ? , choose c vdac = 33 nf = ? + = ? 3.3 10 2.3 5.0 2 15 vdac vdac c r over current setting resistor r ocset the output1 over current limit is 42a and the outpu t2 over current limit is 125a. the ocset bias curre nt calculates out to be 38ua with r osc = 15.8 k (see electrical characteristics table). the total current sense amplifier input offset voltage is typically 0mv. k p, the ratio of inductor peak current over average cur rent in each phase, is calculated with the following equations: 156 .0 1/ 42 )2 10 * 750 12 10 * 150 /( 22.1 ) 22.1 12( / )2 /( ) ( 1 3 9 = ? ? ? ? ? = ? ? ? ? ? = ? n i f v l v v v k limit sw i o o i p 23.0 6 . 41 )2 10 * 750 12 10 * 90 /(5.1 )5.1 12( 2 3 9 = ? ? ? ? ? = ? p k .
IR3523 page 32 of 37 june 20, 2008 the over current set resistor (rocset) can be calcu lated as follows: ocset cs tofst cs p l limit ocset i g v k r n i r / ] ) 1( [ 1 _ ? + + ? ? = , = ? ? = ? ? k 6. 21 ) 10 * 38 /(5. 32 *) 156 .1 10 * 52.0 1 42 ( 6 3 , ocset cs tofst cs p l limit ocset i g v k r n i r / ] ) 1( [ 2 _ ? + + ? ? = , = ? ? = ? ? k 6. 20 ) 10 * 38 /(5. 32 *) 23.1 10 * 47.0 3 125 ( 6 3 . vccl programming resistor r vcclfb1 and r vcclfb2 choose vccl=7v to maximize the converter efficiency . pre-select r vcclfb1 =20k , and calculate r vcclfb2. = ? = ? = k vccl r r vcclfb vcclfb 26.4 23.1 7 23.1 * 10 * 20 23.1 23.1 * 3 1 2 no load offset setting resistor rfb11 and adaptive voltage positioning resistor rdrp11 for output1 given the desired offset voltage (v o_nlofst ) and calculating the fb1 sink current using the equation in the electrical characteristics table, the effective off set resistor value r fb11 can be determined by: = = = = ? ? 523 526 10 * 38 10 * 20 6 3 1 _ 11 fb nlofst o fb i v r (actual value). adaptive voltage positioning lowers the converter v oltage by r o *i o, where r o is the required output impedance of the converter. rdrp11 is calculated with the follow ing equation: = = ? ? = ? ? k r n g r r r o cs room l fb drp 33.1 10 * 6 * 1 5. 32 * 10 * 47.0 * 523 * 3 3 _ 11 11 . in the case of thermal compensation is required, us e equation (14) to (17) to select the r fb network resistors.
IR3523 page 33 of 37 june 20, 2008 layout guidelines the following layout guidelines are recommended to reduce the parasitic inductance and resistance of t he pcb layout, therefore minimizing the noise coupled to t he ic. ? dedicate at least one middle layer for a ground pl ane lgnd. ? connect the ground tab under the control ic to lgn d plane through a via. ? place vccl decoupling capacitor vccl as close as p ossible to vccl and lgnd pins. ? place the following critical components on the sam e layer as control ic and position them as close as possible to the respective pins, r osc , r ocset , r vdac , c vdac , and c ss/del . avoid using any via for the connection. ? place the compensation components on the same laye r as control ic and position them as close as possi ble to eaout, fb, vo and vdrp pins. avoid using any via fo r the connection. ? use kelvin connections for the remote voltage sens e signals, vosns+ and vosns-, and avoid crossing ov er the fast transition nodes, i.e. switching nodes, ga te drive signals and bootstrap nodes. ? avoid analog control bus signals, vdac, iin, and e specially eaout, crossing over the fast transition nodes. ? separate digital bus, clkout, phsout and phsin fro m the analog control bus and other compensation components.
IR3523 page 34 of 37 june 20, 2008 pcb metal and component placement ? lead land width should be equal to nominal part le ad width. the minimum lead to lead spacing should be 0.2mm to minimize shorting. ? lead land length should be equal to maximum part l ead length + 0.3 mm outboard extension + 0.05mm inboard extension. the outboard extension ensures a large and inspectable toe fillet, and the inboard extension will accommodate any part misalignment an d ensure a fillet. ? center pad land length and width should be equal t o maximum part pad length and width. however, the minimum metal to metal spacing should be 0.17mm for 2 oz. copper ( 0.1mm for 1 oz. copper and 0.23mm for 3 oz. copper) ? a single 0.30mm diameter via shall be placed in th e center of the pad land and connected to ground to minimize the noise effect on the ic.
IR3523 page 35 of 37 june 20, 2008 solder resist ? the solder resist should be pulled away from the m etal lead lands by a minimum of 0.06mm. the solder resist mis-alignment is a maximum of 0.05mm and it is recommended that the lead lands are all non solder mask defined (nsmd). therefore pulling the s/r 0.06mm will always ensure nsmd pads. ? the minimum solder resist width is 0.13mm. ? at the inside corner of the solder resist where th e lead land groups meet, it is recommended to provi de a fillet so a solder resist width of 0.17mm remains. ? the land pad should be solder mask defined (smd), with a minimum overlap of the solder resist onto the copper of 0.06mm to accommodate solder resist m is-alignment. in 0.5mm pitch cases it is allowable to have the solder resist opening for the land pad to be smaller than the part pad. ? ensure that the solder resist in-between the lead lands and the pad land is 0.15mm due to the high aspect ratio of the solder resist strip separating the lead lands from the pad land. ? the single via in the land pad should be tented or plugged from bottom boardside with solder resist.
IR3523 page 36 of 37 june 20, 2008 stencil design ? the stencil apertures for the lead lands should be approximately 80% of the area of the lead lands. reducing the amount of solder deposited will minimi ze the occurrence of lead shorts. since for 0.5mm pitch devices the leads are only 0.25mm wide, the s tencil apertures should not be made narrower; openings in stencils < 0.25mm wide are difficult to maintain repeatable solder release. ? the stencil lead land apertures should therefore b e shortened in length by 80% and centered on the le ad land. ? the land pad aperture should be striped with 0.25m m wide openings and spaces to deposit approximately 50% area of solder on the center pad. if too much solder is deposited on the center pad the part will float and the lead lands will be open . ? the maximum length and width of the land pad stenc il aperture should be equal to the solder resist opening minus an annular 0.2mm pull back to decreas e the incidence of shorting the center land to the lead lands when the part is pushed into the solder paste.
IR3523 page 37 of 37 june 20, 2008 package information 40l mlpq (6 x 6 mm body) ja = 18 o c/w, jc = 0.5 o c/w data and specifications subject to change without n otice. this product has been designed and qualified for th e consumer market. qualification standards can be found on ir?s web si te. ir world headquarters: 233 kansas st., el segundo, california 90245, usa t el: (310) 252-7105 tac fax: (310) 252-7903 visit us at www.irf.com for sales contact informati on

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